Front end for full duplex cable modem

ABSTRACT

Designs for a front end for suppressing adjacent channel interference (ACI) and adjacent leakage interference (ALI) in a full duplex cable modem (CM) for a Data Over Cable Service Interface Specification (“DOCSIS”) network are described. The CM includes an upstream (US) signal path receiving a digital US input signal and transmitting an analog-converted US signal in a US frequency range to a cable modem termination system (CMTS); a downstream (DS) signal path receiving an analog DS signal in a DS frequency range and converting the analog DS signal into a digital DS signal; and an echo cancellation (EC) circuit configured to subtract, from at least one of the analog DS signal and the digital DS signal, a correction signal generated from the digital US input signal or a correction signal generated from the analog-converted US signal to generate an echo-cancelled digital DS input signal without ACI and ALI.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of priority under 35 U.S.C. § 119(e)to U.S. Provisional Application Ser. No. 62/447,148 entitled “FRONT ENDFOR FULL DUPLEX CABLE MODEM,” filed Jan. 17, 2017, which is herebyincorporated by reference in its entirety.

TECHNICAL FIELD

This disclosure relates in general to the field of communicationsnetworks and, more particularly, to a design for a front end forimplementing a full duplex (FDX) cable modem (CM) for a Data Over CableService Interface Specification (“DOCSIS”) network.

BACKGROUND

Consumer appetite for bandwidth continues to grow exponentially in thecable network market. In some cable network architectures, includingremote physical layer (RPHY) with digital fiber, the coax fiber becomesthe bottleneck in throughput, stifling increase in bandwidth. Thetypical multi-system operator (MSO) is out of options currently, due tothe inherent technological limitations of existing cable networkcomponents. For example, the Shannon channel capacity limit (e.g., tightupper bound on rate at which information can be reliably transmittedover a communications channel) has practically been achieved already inexisting cable network architectures. There is consumer driven demand toextend the frequency spectrum beyond 1.2 GHz, but a conventionalextension would require extensive network upgrade. Although technologyexists, upgrades in network components are limited by capitalexpenditure budget limitations, in particular for all optics fiber tothe home (FTTH). In such scenarios, it may be desirable to offer newservices with full downstream/upstream (DS/US) throughput, e.g.,matching Gigabit-capable Passive Optical Networks (GPON) standard of 2.5Gbits downstream and 1 Gbits upstream with limited capital expenditurefor outside plant upgrade.

BRIEF DESCRIPTION OF THE DRAWINGS

To provide a more complete understanding of the present disclosure andfeatures and advantages thereof, reference is made to the followingdescription, taken in conjunction with the accompanying figures, whereinlike reference numerals represent like parts, in which:

FIG. 1 is a simplified block diagram illustrating a communication systemwith a full duplex network architecture in cable network environments;

FIG. 2 is a simplified block diagram illustrating example details ofembodiments of a cable modem termination system (CMTS) of thecommunication system;

FIG. 3 is a simplified block diagram illustrating another exampledetails of embodiments of the CMTS of the communication system;

FIG. 4 illustrates D3.1 CM fidelity specifications for adjacent channelspurious emission;

FIG. 5 illustrates self-interference at a CM;

FIG. 6 is a simplified block diagram of a first example embodiment of acircuit echo cancellation (EC) at a CM;

FIG. 7 illustrates self-interference at a CM with receive (RX) filteringand echo cancellation;

FIG. 8 is a simplified block diagram illustrating notch filters tosuppress upstream (US) in-band signals;

FIG. 9 illustrates an example spectrum allocation for FDXcommunications;

FIG. 10 illustrates eight example combinations of CM downstream (DS)path filters for the FDX bands shown in FIG. 10;

FIG. 11 is a simplified block diagram showing a DS filter block withswitchable high-pass (HPF) and low-pass (LPF) filters;

FIG. 12 is a simplified block diagram of an alternative DS filter blockwith a cascaded arrangement of filters;

FIG. 13 is a simplified block diagram of a system for providing analogEC with digital assist;

FIG. 14 is a simplified block diagram of a system for providing analogand digital EC; and

FIG. 15 is a schematic flow diagram depicting processes executed by thesystems illustrated in FIGS. 6 and 13.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS Overview

Numerous interference issues occur at cable modems (“CMs”) that supportfull duplex (“FDX”) operations. Such interference issues may result fromboth the upstream (“US”) transmissions of neighboring CMs and UStransmissions of the CM itself. The latter will be referred to asself-interference.

Embodiments described herein include techniques for increasing thedynamic range of a full duplex (“FDX”) endpoint, including filteringtechniques to accomplish that end. Embodiments described herein furtherinclude switched filter implementation, shifting the frequencies of thefilters so as not to impede the data path, moving filters out of thedata path using analog and digital echo cancellation (“EC”) and usinganalog EC for suppressing Adjacent Channel Interference (“ACI”) anddigital EC for suppressing Adjacent Leakage Interference (“ALI”).Techniques in connection with embodiments described herein may also beapplied to wireless communications technologies.

In certain embodiments, there are two techniques that the CM mayimplement to mitigate self-interference issues, including adding afilter at the receiver to suppress the interferences to maintainreceiver dynamic range (reduce the headroom for interference) tomitigate Adjacent Channel Interference ACI and implement EC at the CM tomitigate Adjacent Leakage Interference (ALI).

Example Embodiments

Turning to FIG. 1, FIG. 1 is a simplified block diagram illustrating acommunication system 10 enabling full duplex network communication incable network environments in accordance with one example embodiment.FIG. 1 illustrates a cable network 12 (indicated generally by an arrow)facilitating full duplex communication between a cable modem terminationsystem (CMTS) 14 and one or more cable modems (CMs) 16. Network 12includes transceivers 18, amplifiers 20, and taps and splitters 22. CMTS14 includes an intelligent media access control (MAC) scheduler 26 thatenables transmission-reception (T-R) coordination for interferenceavoidance, along with a processor 27 and a memory element 28 thatfacilitate executing instructions residing in MAC scheduler 26. Invarious embodiments, cable modems 16 may be grouped into variousinterference groups 30 to enable full duplex communication with littleto no interference. Groups 30 may comprise radio frequency (RF) isolatedgroups that allow frequency re-use through intelligent MAC scheduling.

Transceivers 18 enable full band communication for both upstream (US)and downstream (DS) network traffic and implement dynamic interferencecancellation, also referred to herein as adaptive interferencecancellation (AIC). Note that as used herein, the term “upstream” (orUS) refers to a communication direction from cable modems 16 towardsCMTS 14; the term “downstream” (or DS) refers to a communicationdirection from CMTS 14 towards cable modems 16. Amplifiers 20 enablefull band communication for both upstream and downstream networktraffic, and implement AIC with e.g. echo suppression. Taps andsplitters 22 may enable full band communication for downstream andupstream traffic.

Each of the cable modems 16 supports full band communication, butoperates in simplex mode for upstream or downstream transmission. Forexample, each of cable modems 16 may be assigned non-overlappingfrequency bands for upstream and downstream communication, yet the sameset of carriers can be used for the downstream and upstreamcommunication, yielding a doubling of throughput compared to currentlyexisting non-full duplex systems. Communication system 10 can enablehigher bandwidth (e.g., bandwidth is the maximum amount of data that cantravel through a communication channel) and throughput (e.g., throughputrefers to the quantity of data that actually does travel through thecommunication channel successfully) through full-duplex communication.Various aspects of the communication network 10 and its operation aredescribed in commonly assigned US Patent Application having thepublication number 2017/0019146 which is incorporated herein byreference in its entirety.

To explain generally, bandwidth limitations are solved in somecommunication networks through duplex communication. In a general sense,duplex communication is bidirectional, allowing both end nodes of acommunication channel to send and receive data simultaneously and one ata time. Both end nodes have the ability to operate as sender andreceiver at the same time, or take turns sending or receiving data.Duplex-based systems typically have dual communication channels thatprovide separate paths for upstream (US) (e.g., uplink, outgoing,transmitting) and downstream (DS) (e.g., downlink, incoming, receiving)communication. In full duplex mode, the node sends and receives signalssimultaneously in the same frequency range.

Examples of communication techniques include frequency divisionduplexing (FDD) and time division duplexing (TDD). In FDD, separatefrequency bands (e.g., carrier frequencies) are used at the transmitterand receiver. Because FDD uses different frequency bands for upstreamand downstream operations, the upstream and downstream communication donot interfere with each other.

Full duplex communication mechanisms that are not FDD or TDD have notbeen used in cable networks, because the inherent network architectureand communication protocols do not support such communicationmechanisms. For example, half-duplex cable between CMTS and CMs wasfirst introduced in the United States in the late 1950s. In recentyears, cable operators have been investing heavily to upgrade cablesfrom half-duplex to full-duplex as a necessary first step to capitalizeon the demand for integrated data and voice services. However, upstreamtransmissions still continue to have a slower transmission rate thandownstream receptions.

Nevertheless, with a properly configured cable network architecture,such as cable network 12 of communication system 10, full duplexcommunication can drastically expand available upstream spectrum andprovide near symmetric downstream and upstream throughput. Systemcapacities (e.g., bandwidth) can improve with full duplex communication.Moreover, full duplex communication may be technology-agnostic and/orstandards-agnostic.

However, implementing full duplex in existing cable networks meet withcertain challenges. For example, a large transmitted signal coupled backto the receiver due to reflection (e.g., self-interference from thetransmit pathway into the receive pathway within one and sametransceiver) at any of the network components, including CMTS 14, cablemodems 16, transceivers 18, amplifiers 20 and taps and splitters 22, canoverwhelm the received signal at the receiver.

Embodiments of communication system 10 can resolve such issues byenabling full duplex communication using appropriately configuredcomponents and spectrum sharing techniques. Full duplex communicationcan be successfully implemented by suppressing (e.g., eliminating)transmitted signals that are coupled back to the receiver (e.g., as anecho, as an upstream signal leaking into the downstream pathway and viceversa, etc.). Sufficient transmitted signal cancellation and/orelimination can be achieved by leveraging (among other parameters) stateof the art devices and digital signal processing technologies, highspeed and high performance (e.g., high resolution) analog-to-digitalconverters (ADC), devices with more signal processing capability, an AICscheme which mitigates Adjacent Channel Interference (ACI) and AdjacentLeakage Interference (ALI), and advanced MAC scheduling for spectrumsharing. In various embodiments, the AIC scheme suppresses at a receiver(for example transceiver 18 or amplifier 20) a signal transmitted by atransmitter (of transceiver 18 or amplifier 20, respectively). Further,in addition to the AIC scheme, full band amplifier 20 may implement echocancellation (EC).

Interference cancellation can be achieved, for example, through advanceddigital signal processing algorithms. Full duplex is independent ofcable access technologies and high layer architectures; thus, it canwork with any high level protocols and architectures. Full duplex can beused with existing access technology or as a candidate for nextgeneration DOCSIS access technology. Full duplex is novel andsubstantial, and has business and technology impacts that may go beyondcable access (wireless, for example).

In an example embodiment, the frequency spectrum of cable network 12 maybe divided into multiple frequency ranges (see for example FIG. 9). Insome embodiments, each frequency range aligns with a channel boundary.For each specific one of cable modems 16 and each frequency range, MACscheduler 26 may identify those cable modems 16 whose upstreamtransmissions interfere with downstream receptions of that specific oneof cable modems 16, and those cable modems 16 whose downstreamreceptions are interfered by upstream transmissions of that specific oneof cable modems 16, if they operate on that same frequency. Based onsuch identification, MAC scheduler 26 avoids assigning cable modems 16to frequency ranges that may cause interferences among them. Cablemodems 16 operate with FDD and no neighboring cable modems 16 areassigned to overlapping downstream and upstream frequency ranges.

Turning to FIG. 2, FIG. 2 is a simplified block diagram illustratingexample details of transceiver 18 of the CMTS 14 according to anembodiment of communication system 10. In various embodiments, each ofdownstream and upstream signals uses the complete frequency spectrumduring full duplex communication. As a result, a transmitted signal 162(comprising downstream data from CMTS 14 to cable modems 16) and areceived signal 164 (comprising upstream data from cable modems 16 toCMTS 14) overlap in frequency and time at transceiver 18. Typically,transmitted signal 162 has a higher signal level (e.g., with more power)than received signal 164, and can completely overwhelm the receivedsignal 164 if there is insufficient isolation between a transmitterportion 166 and a receiver portion 168 of transceiver 18. In variousembodiments, to enable full duplex communication in cable network 12,interferences from transmitter portion 166 may be suppressed at receiverportion 168 using an AIC algorithm implemented in a digital signalprocessor (DSP) 170 in transceiver 18. DSP 170 includes a memory elementfor storing instructions and data appropriately. A clock module 171facilitates timing functions for the AIC algorithm. In variousembodiments, clock module 171 may be embedded in DSP 170. DSP 170 may beconfigured to perform FFT/IFFT (Fast Fourier transform/inverse FastFourier transform) or other standard DSP operations. Embedded processorsfor control operations and I/O operations, with support for floatingpoint operations may also be included in DSP 170. It will be understood,although not explicitly shown in FIG. 2, that a comparable DSP oranother processor storing functions of the AIC algorithm may also beincorporated in cable modems 16.

Turning to FIG. 3, FIG. 3 illustrates in more detail that downstreamsignal 162 transmitted from the CMTS may be reflected back totransceiver 18 on an upstream pathway 180 in one or more frequenciesthat overlap with those of signals in upstream pathway 180 due to fullduplex operation. Upstream pathway 180 refers to portions of transceiver18 that include communication pathway of upstream signals (to CMTS 14from cable modems 16). Thus, the reflected signal may interfere withanother upstream transmission (e.g., from cable modems 16) on upstreampathway 180, generating upstream signal 164, comprising the upstreamtransmission interfered by the reflected signal. In various embodiments,it may be desirable to extract the upstream transmission without theinterferences from the reflected signal. The interactions between thetransmitted signal and the reflected signal can be problematic and haveto be addressed not only at the CMTS 14, but also at the various modems16 themselves.

With regard to noise, in Common Channel Interference (“CCI”), a “bad”signal overlaps a “good” signal; in Adjacent Leakage Interference (ALI),a “bad” signal creates a noise floor; and in Adjacent ChannelInterference (ACI), a “bad” signal ruins a “good” signal AGC and dynamicrange. Currently, the plan is to eliminate CCI with scheduling by MACscheduler 26 (FIG. 1), eliminate ALI and ACI with filtering, and usefiltering to help reduce self and adjacent interference. In accordancewith embodiments described herein, ALI may be eliminated with digitalEC, and ACI may be eliminated with filtering or analog EC and byrefining filtering to allow more scheduling combinations. Embodimentsherein focus on self-interference and thus exclude interference causedby other modems.

Turning to FIG. 4, current D3.1 CM fidelity specifications require thatadjacent channel spurious emission must meet ≈44dBr with total FDXbandwidth (“BW”)=576 MHz. With regard to interference from neighboringCMs, downstream (“DS”) reception on an adjacent channel may be impactedby both ACI and ALI, as shown in FIG. 5 and should be mitigated.

In certain embodiments, the CM may implement two techniques to mitigateself-interference issues, including adding a filter at the CM side tosuppress the interferences to maintain the dynamic range of the CMreceiver (reduce the headroom for interference), in particular theanalog-to digital converters (ADC), to mitigate Adjacent ChannelInterference (ACI) and implement EC at the CM to mitigate AdjacentLeakage Interference (ALI). These techniques are illustrated in FIGS. 6and 7, with FIG. 6 showing a simplified block diagram illustrating echocancellation (EC) at a CM to mitigate Adjacent Leakage Interference(ALI) issues and FIG. 7 illustrating example signal strengths ofself-interference at a CM with receive (RX) filtering of DS signals andecho cancellation.

Turning now more specifically to FIG. 6, FIG. 6 illustrates a firstexample embodiment A US signal is transmitted by the CM to a HFC (hybridfiber coax) and a DS signal is received by the CM from the HFC. Thedigital US signal is first converted to an analog signal in adigital-to-analog converter (DAC) 612 and modulated on a RF baseband.The RF signal is then amplified by amplifier 614, which may be alow-noise amplifier (LNA), and passed through a low-pass filter (LPF)616 to limit spurious out-of-band (OOB) signals above the upper limit of684 MHz for the exemplary FDX frequency band. A conventional isolator610 provides isolation between the US and DS channels and galvanicisolation between the CM and the HFC. In the illustrated example, the DSsignal received from the HFC is filtered by a filter or filter block620, which may have a switched filter arrangement, which will bedescribed in more detail below in FIGS. 10-12, and which passesfrequencies in the transmission band(s) of the DS signal. DS filter orfilter block 620 limits ACI by passing the DS signal and removing mostof the US signal. The filtered DS signal may then be amplified inamplifier 621 and converted into a digital DS signal inanalog-to-digital converter (ADC) 622. To provide echo cancellation, aportion of the US signal modulated on the RF baseband is tapped in theanalog US signal path. This tapped signal is then digitized in ADC 618and provided to a digital EC circuit 624. Before being digitized, thetapped signal may be passed through a notch filter 626 to attenuate thechannel(s) in the frequency range of the transmitted US signal. The stopand pass bands, respectively, of the notch filter 626 and the filterblock 620 will be described in more detail below with reference to FIG.10. The digitized DS signal is also provided to the digital EC circuit624, which performs echo cancellation by suitably subtracting thedigitized signal from ADC 618 from the digitized signal from ADC 622.Digital EC 624 limits ALI and may stop around 800 MHz. The functionalityof digital echo cancellation and the circuits employed therefor areknown in the art and will therefore not be described herein.

The filters in filter block 620 do not need a fast roll-off, since thefilter roll-off regions can be in US bands, as long as the filterssufficiently suppress the US signal to keep the total interference levelunder a targeted threshold; e.g., 6 dB interference to received signalratio (see also FIG. 5). The receiver filters in filter block 620 do notcause spectrum loss, as their roll-off regions are in US paths, asillustrated in FIG. 7.

The notch filter 626 used to suppress US in-band signals preserves thedynamic range of ADC 618 (i.e., avoids adding ADC noise to the desiredDS signal noise floor). The stop band of the notch filter 626 may beselected commensurate with the frequency band for US transmission.Turning now to FIG. 8, FIG. 8 shows an example cascaded arrangement ofnotch filters 626 ₁, 626 ₂, 626 ₃ having different frequency bands forUS transmission, as illustrated in FIG. 9, that can be switched in orout as needed depending on the current US transmission configuration.Stated differently, a filter is switched on only when its notchedspectrum or stopband is assigned for US transmission. The losses of thefilters and the switches are not of concern, as these filters are not inthe CM receive path. The indicated example stopbands are for an examplespectrum allocation for FDX communications in the frequency rangesbetween 108 MHz and 684 MHz to be described below with reference to FIG.9, but may be adapted to other frequency ranges depending on the overallspecification of the communication system 10. Suitable switches capableof operating in frequency ranges from 5 MHz to 6 GHz with insertionlosses of 0.3 dB at approximately 1 GHz are commercially available.

Turning now to FIG. 9, FIG. 9 illustrates an example spectrum allocationfor FDX communications spanning the frequency range betweenapproximately 108 MHZ and 684 MHz. The exemplary FDX band is subdividedinto six frequency channels, each channel extending over approximately96 MHz. The number-triple on the left-hand side of FIG. 9 refers toadjacent frequency channel pairs which are allocated as follows: A value“1” indicates an upstream (US) channel pair and the value “0” indicatesa downstream channel pair. For example, {100} indicates that channels 1and 2 from 106-300 MHZ are US paths and channels 3 through 6 from300-684 MHZ are DS paths. Likewise, {110} indicates that channels 1through 4 from 106-492 MHZ are US paths and channels 5 and 6 from492-684 MHZ are DS paths. As mentioned above, the channel allocation forFDX operation is merely exemplary and may be extended to other, forexample higher frequencies as needed.

FIG. 10 illustrates filter combinations for eight unique CM DS pathfilters, which block US frequency bands and pass DS frequency bands. Thenumber-triples shown in FIG. 10 correspond to those in FIG. 9.Accordingly, {100} indicates that channels 3 through 6 from 300-684 MHZare DS paths, so that any DS signal with a frequency greater than 300MHz is passed by the 300 MHz HPF. Likewise, {110} indicates thatchannels 5 and 6 from 492-684 MHZ are DS paths, so that any DS signalwith a frequency greater than 492 MHz is passed by the 492 MHz HPF.{010} indicates that channels 1 and 2 from 108 MHz to 300 MHz andchannels 5 and 6 from 492-684 MHZ are DS paths, so that any DS signalwith a frequency greater than 492 MHz is passed by the 492 MHz HPF andthe cascaded 108 MHz HPF and the 300 MHz LPF operate as a 108 MHz-300MHz bandpass filter for the DS signal.

FIG. 11 is a simplified block diagram showing a first embodiment of aswitched DS filter block 620. The circuit illustrated in FIG. 11implements all eight filter combinations shown in FIG. 10, with a totalof six filters (4 high-pass filters (HPF) operating at frequencies of108 MHz, 300 MHz, 492 MHz and 684 MHz, and 2 low-pass filters (LPF)operating at frequencies of 300 MHz and 492 MHz, as well as five RFswitches 1101, 1102, 1103, 1104, 1105. The switched DS filter block 620,which has nearly the equivalent complexity and cost of two switchingdiplexers, is simple and inexpensive to implement.

Suitable RF switches capable of operating in frequency ranges from 5 MHzto 6 GHz with insertion losses of 0.3 dB at approximately 1 GHz arecommercially available.

FIG. 12 is a simplified block diagram showing a second embodiment of aswitched DS filter block 620 with a cascaded arrangement of filters,which are switched in and out by RF switches 1201, 1202, 1203, 1204,1205. The circuit illustrated in FIG. 12 likewise realizes all eightfilter combinations shown in FIG. 10. The roll-off is additive, so thatthe roll-off at 684 MHz is steeper than the roll-off at 108 MHz. Whilecascading simplifies each individual filter because lower-Q filters canbe used, the overall insertion loss may disadvantageously increase.

Turning now to FIG. 13, FIG. 13 is a simplified block diagram of acircuit 1300 for providing analog and digital EC. The circuit 1300 canbe best understood by partitioning the circuit 1300 into four branchesthat perform different functions. The 1^(st) branch (top) receives theDS signal from the CMTS via the HFC by way of isolator 610, as describedabove with reference to FIG. 6. The DS signal passes through an analogEC circuit 1320, amplifier 621 and ADC 622 to digital EC circuit 624.The analog EC circuit 1320 performs the role of filter block 620 in thereceive (DS signal) path of FIG. 6. In all other aspects, the 1^(st)branch is equivalent to the DS signal path of FIG. 6. The lower portionof the 4^(th) branch (bottom) transmits the US signal to the CMTS viathe HFC by way of isolator 610 and is thus equivalent to the US signalpath of FIG. 6.

The analog EC circuit 1320 performs echo cancellation, i.e. limits orsuppresses ACI, by subtracting a suitably processed portion of the USsignal from the received analog DS signal. DSP 1328 generates from theUS signal a 180° out-of-phase signal, which may be delayed and which isthen converted to an analog signal in DAC 1312, amplified in amplifier1314 and low-pass filtered in LPF 1316 to eliminate OOB signals. In thisway, signal components of the US signal are substantially eliminatedfrom the signal that is subsequently supplied by the analog EC 1320 tothe amplifier 621 and the circuits downstream of the amplifier 621.

Analog EC circuits are known in the art and described, for example, inIEEE Journal of Solid-State Circuits, Vol. 36, No. 3 (2001), pp 366-373.The analog EC circuit 1320 may require a training period which mayproceed in two phases. In phase 1, a step is applied and a tap locatorcircuit calculates the impulse response, identifying the significanttaps. In phase 2, random data is applied and a LMS (least-mean-square)algorithm adapts the finite-response (FIR) coefficients to minimize theresidual echo. After phase 2, the circuit is ready for full-duplex datacommunication. There will be some retraining required for the ECcoefficients of analog EC circuit 1320 when the channel configurationchanges. Hardware variations on filters (notch filter 626 and the filterblock 620) will be absorbed by the EC coefficient training.

While the analog EC circuit 1320 can be of simple design and can limitACI from amplifier 1314 and may also eliminate ALI, a digital EC circuit1324 may still have to be employed to cancel or at least amelioratenoise and nonlinearities introduced by other electronic circuits of theCM, such as low-noise amplifier 614 and the DACs 612, 1312. The digitalEC circuit 1324 limits or suppresses ALI.

In the 2^(nd) branch of FIG. 13, the signal supplied by LPF 1316 to theinput of the analog EC circuit 1320 is tapped and passed through a notchfilter 1326 that blocks signals in the US frequency range. The signal isthen digitized in ADC 1318 and supplied to digital EC circuit 1324 inorder to remove from the analog-filtered signal any noise and/ornonlinearities introduced in the analog EC circuit 1320 by the DSP 1328,the DAC 1312 and amplifier 1314, which would otherwise impair the DSsignal. Notch filter 1326 maintains the dynamic range of the ADC 1318 tokeep the noise floor low.

The 3^(rd) branch of FIG. 13 is designed similar to the 2^(nd) branchand includes a notch filter 626 that like notch filter 1326 in the2^(nd) branch blocks signals in the US frequency range. As in FIG. 6, aportion of the US signal modulated on the RF baseband is tapped at theanalog US signal path. This tapped signal is then, as in FIG. 6, passedthrough the notch filter 626 to attenuate the channel(s) in thefrequency range of the RF baseband, digitized in ADC 618 and provided todigital EC circuit 1324. The 3^(rd) branch is employed to cancel echoesoriginating, for example, from DAC 612 and amplifier 614 in the transmit(US) signal branch.

The analog EC circuit 1320 in the aforedescribed example is designed tooperate up to frequencies of 684 MHz. The digital EC circuit operates toapproximately 800 MHz. Notch filters maintain good dynamic range on ADCs618, 1318 to keep the noise floor low. The analog EC circuit 1320obviates the need for switched filters 620 in the US or DS signal path.DSP/EC coefficient training can absorb manufacturing variations in thefilter block 620 in FIG. 6.

Turning now to FIG. 15, FIG. 15 is a schematic process flow diagramdepicting a process 1500 that employs the systems shown in FIG. 6 andFIG. 13 for limiting or removing ACI and ALI in a CM. The process startsat step 1501, with the CM transmitting, at step 1502, a US signal to theCMTS via the HFC. The CM also receives a DS signal from the CMTS via theHFC, at step 1503. The DS is either filtered to block frequencies in thefrequency range of the US signal, at step 1504, as described above withreference to FIG. 6, or subtracts from received DS signal in analog ECcircuit one or more digitally processed US signals that have beenconverted to an analog signal, at step 1505, as described above withreference to FIG. 13. The filtered DS signal or the DS signal outputtedby the analog EC circuit, respectively, is then digitized, and spurioussignals outside US frequency range are thereafter digitally subtractedfrom the digitized DS signal in a digital EC circuit, at step 1507. ACIand ALI are thereby limited or suppressed in the output signal generatedby the digital EC circuit, at step 1508. The process 1500 ends at step1509.

Turning now to FIG. 14, FIG. 14 illustrates another example embodimentof a circuit 1400 at a CM for EC. Circuit 1400 employs an analog ECcircuit 1320 with digital assist from a digital signal processor (DSP)1424. The path for the US signal includes, as in circuit 600 of FIG. 6,DAC 612, amplifier 614, and LPF 616. LPF 616 in the US signal pathlimits spurious OOB (out-of-band) signals. Analog EC 1320 cooperateswith DSP 1324 to eliminate ACI and ALI originating from amplifier 614.

The DS signal is supplied to analog EC circuit 1320. The output fromanalog EC circuit 1320 is then amplified in amplifier 621 and convertedinto a digital DS signal in ADC 622. As in FIGS. 6 and 13, a portion ofthe low-pass-filtered US signal is tapped at the analog US signal pathand optionally passed through a notch filter 626 to attenuate thechannel(s) in the frequency range of the transmitted US signal andthereafter digitized in ADC 618. Instead of a digital EC circuit 624(FIG. 6) or 1324 (FIG. 13), circuit 1400 employs a digital signalprocessor (DSP) 1424, which receives the digitized output signal fromDAC 618 and compares the received digitized output signal with the DSoutput signal from ADC 622. The DSP 1424 then generates a suitablyshaped and/or time-shifted correction signal which is then supplied toDAC 1412, where the correction signal is converted into an analogsignal, amplified in amplifier 1414 and subtracted in analog EC circuit1320 from the received analog DS signal. The coefficients of the DSP1424 are adjusted until adequate echo cancellation is achieved and ACIand ALI are eliminated or at least limited. The design of circuit 1400assumes that amplifier 1414 (LNA2) is lower power than amplifier 614(LAN1) and that spurious OOB from amplifier 1414 is sufficiently small.The design furthermore requires that the dynamic range of the ADCs andDACs is quite high, which may make circuit 1400 less attractive.

Note that in this Specification, references to various features (e.g.,elements, structures, modules, components, steps, operations,characteristics, etc.) included in “one embodiment”, “exampleembodiment”, “an embodiment”, “another embodiment”, “some embodiments”,“various embodiments”, “other embodiments”, “alternative embodiment”,and the like are intended to mean that any such features are included inone or more embodiments of the present disclosure, but may or may notnecessarily be combined in the same embodiments. Furthermore, the words“optimize,” “optimization,” and related terms are terms of art thatrefer to improvements in speed and/or efficiency of a specified outcomeand do not purport to indicate that a process for achieving thespecified outcome has achieved, or is capable of achieving, an “optimal”or perfectly speedy/perfectly efficient state.

In some embodiments, at least some portions of the architecturesoutlined herein may be implemented in software. In some embodiments, oneor more of the described features may be implemented in hardware,provided external to these elements, or consolidated in any appropriatemanner to achieve the intended functionality. The various components mayinclude software (or reciprocating software) that can coordinate inorder to achieve the operations as outlined herein. In still otherembodiments, these elements may include any suitable algorithms,hardware, software, components, modules, interfaces, or objects thatfacilitate the operations thereof.

Furthermore, CMTS 14, CM 16, and other components described and shownherein (and/or their associated structures) may also include suitableinterfaces for receiving, transmitting, and/or otherwise communicatingdata or information in a network environment. In a general sense, thearrangements depicted in the FIGURES may be more logical in theirrepresentations, whereas a physical architecture may include variouspermutations, combinations, and/or hybrids of these elements. It isimperative to note that countless possible design configurations can beused to achieve the operational objectives outlined here. Accordingly,the associated infrastructure has a myriad of substitute arrangements,design choices, device possibilities, hardware configurations, softwareimplementations, equipment options, etc.

In some of example embodiments, one or more memory elements (e.g.,memory element 28 in the CMTS or a similar unillustrated memory elementin CM 16) may store data used for the operations described herein.Furthermore, the memory element may be able to store instructions (e.g.,software, logic, code, etc.) in non-transitory media, such that theinstructions are executed to carry out the activities described in thisSpecification. A processor can execute any type of instructionsassociated with the data to achieve the operations detailed herein inthis Specification. The activities outlined herein may be implementedwith fixed logic or programmable logic (e.g., software/computerinstructions executed by a processor) and the elements identified hereincould be some type of a programmable processor, programmable digitallogic (e.g., a field programmable gate array (FPGA), an erasableprogrammable read only memory (EPROM), an electrically erasableprogrammable read only memory (EEPROM)), an ASIC that includes digitallogic, software, code, electronic instructions, flash memory, opticaldisks, CD-ROMs, DVD ROMs, magnetic or optical cards, other types ofmachine-readable mediums suitable for storing electronic instructions,or any suitable combination thereof.

These devices may further keep information in any suitable type ofnon-transitory storage medium (e.g., random access memory (RAM), readonly memory (ROM), field programmable gate array (FPGA), erasableprogrammable read only memory (EPROM), electrically erasableprogrammable ROM (EEPROM), etc.), software, hardware, or in any othersuitable component, device, element, or object where appropriate andbased on particular needs. The information being tracked, sent,received, or stored in communication system 10 or CM 16 could beprovided in any database, register, table, cache, queue, control list,or storage structure, based on particular needs and implementations, allof which could be referenced in any suitable timeframe.

It is also important to note that the operations and steps describedwith reference to the preceding FIGURES illustrate only some of thepossible scenarios that may be executed by, or within, the system. Someof these operations may be deleted or removed where appropriate, orthese steps may be modified or changed considerably without departingfrom the scope of the discussed concepts. In addition, the timing ofthese operations may be altered considerably and still achieve theresults taught in this disclosure. The preceding operational flows havebeen offered for purposes of example and discussion. Substantialflexibility is provided by the system in that any suitable arrangements,chronologies, configurations, and timing mechanisms may be providedwithout departing from the teachings of the discussed concepts.

Although the present disclosure has been described in detail withreference to particular arrangements and configurations, these exampleconfigurations and arrangements may be changed significantly withoutdeparting from the scope of the present disclosure. For example,although communication system 10, HFC and CM's 16 have been illustratedwith reference to particular elements and operations that facilitate thecommunication process, these elements, and operations may be replaced byany suitable architecture or process that achieves the intendedfunctionality of communication system 10, HFC and CM's 16.

Numerous other changes, substitutions, variations, alterations, andmodifications may be ascertained to one skilled in the art and it isintended that the present disclosure encompass all such changes,substitutions, variations, alterations, and modifications as fallingwithin the scope of the appended claims. In order to assist the UnitedStates Patent and Trademark Office (USPTO) and, additionally, anyreaders of any patent issued on this application in interpreting theclaims appended hereto, Applicant wishes to note that the Applicant doesnot intend, by any statement in the specification, to limit thisdisclosure in any way that is not otherwise reflected in the appendedclaims.

What is claimed is:
 1. A full-duplex cable modem (CM), comprising: anupstream (US) signal path receiving a digital US input signal andtransmitting an analog-converted US signal in a US frequency range to acable modem termination system (CMTS); a downstream (DS) signal pathreceiving an analog DS signal in a DS frequency range and converting theanalog DS signal into a digital DS signal; and an echo cancellation (EC)circuit configured to subtract, from at least one of the analog DSsignal and the digital DS signal, a correction signal generated from thedigital US input signal or from the analog-converted US signal togenerate an echo-cancelled digital DS input signal.
 2. The full-duplexcable modem of claim 1, wherein the full-duplex cable modem is connectedto the CMTS by way of a hybrid fiber coax (HFC).
 3. The full-duplexcable modem of claim 1, wherein the analog-converted US signal ismodulated on a baseband (BB) carrier.
 4. The full-duplex cable modem ofclaim 1, wherein the DS signal path comprises a filter block havingswitchable filter combinations with one or more pass-bands in the DSfrequency range and operates to limit adjacent-channel-interference(ACI).
 5. The full-duplex cable modem of claim 1, wherein the EC circuitis implemented as a digital EC circuit and digitally subtracts thecorrection signal from the digital DS signal to limit Adjacent LeakageInterference (ALI).
 6. The full-duplex cable modem of claim 5, furthercomprising a first notch filter receiving the analog-converted US signaland configured to block signals in the US frequency range beforeanalog-to-digital conversion to a digitized correction signal.
 7. Thefull-duplex cable modem of claim 1, wherein the EC circuit isimplemented as an analog EC circuit receiving the analog DS signal,wherein the correction signal is an analog correction signal derivedfrom the digital US input signal and processed in a digital signalprocessor (DSP), and supplied to the analog EC circuit afterdigital-to-analog conversion.
 8. The full-duplex cable modem of claim 7,further comprising a second notch filter receiving the analog correctionsignal and configured to block signals in the US frequency range beforeanalog-to-digital conversion of the correction signal to a seconddigitized correction signal.
 9. The full-duplex cable modem of claim 1,wherein the EC circuit is implemented as an analog EC circuit receivingthe analog DS signal, wherein the correction signal is derived from theanalog-converted US signal and processed in a digital signal processor(DSP), and supplied to the analog EC circuit after digital-to-analogconversion.
 10. The full-duplex cable modem of claim 1, wherein the USsignal path comprises a first DAC, a first amplifier and a firstlow-pass filter; the DS signal path comprises an analog EC circuitreceiving the analog DS signal, a second amplifier, a first ADC and adigital EC circuit; the analog EC circuit configured to subtract fromthe analog DS signal an analog correction signal derived from thedigital US input signal after passing the digital US input signalthrough a DSP, a second DAC, a second amplifier and a low-pass filter,wherein the analog EC limits ACI; the digital EC circuit configured tosubtract from the digital DS signal a first digital echo correctionsignal generated from the analog-converted US signal which is filteredby a first notch filter to eliminate spurious signals in the USfrequency range, and subtracting from the digital DS signal a seconddigital echo correction signal generated from the analog correctionsignal which is filtered by a second notch filter to eliminate spurioussignals in the US frequency range, wherein the digital EC limits ALI,with the digital EC circuit outputting an echo-cancelled digital DSsignal.
 11. The full-duplex cable modem of claim 2, wherein the HFC ispart of a network operating in accordance with a Data Over Cable ServiceInterface Specification (DOCSIS).
 12. A method of operating afull-duplex cable modem (CM), comprising: converting a digital upstream(US) signal into an analog US signal in a US frequency range; receivingan analog downstream (DS) signal in a DS frequency range; analogfiltering the received DS signal; digitizing the analog-filtered DSsignal; tapping the transmitted analog US signal; digitizing the tappedanalog US signal; and digitally subtracting from the digitized DS signalat least a portion of the digitized US signal.
 13. The method of claim12, wherein analog filtering comprises bandpass-filtering the receivedDS signal by passing signals in the DS frequency range and rejectingsignals the US frequency range.
 14. The method of claim 12, whereinanalog filtering comprises subtracting from the received analogdownstream DS signal a digitally processed analog correction signalderived from the converted analog US signal.
 15. The method of claim 12,wherein analog filtering comprises subtracting from the received analogdownstream DS signal an analog correction signal derived from thedigital US signal, wherein the digital US signal is processed in a DSPbefore being converted to the analog correction signal.
 16. The methodof claim 15, further comprising notch-filtering the analog correctionsignal to reject signals in the US frequency range and digitizing thefiltered analog correction signal, and subtracting the digitizedcorrection signal from the digitized DS signal.
 17. The method of claim16, further comprising bandpass-filtering at least a portion of thelow-pass filtered processed analog signal by passing signals in the DSfrequency range and rejecting signals the US frequency range, digitizingthe bandpass-filtered signal and digitally subtracting the digitizedbandpass-filtered signal from the received digitized DS signal.
 18. Acomputer program having program instructions stored on a tangiblenon-transitory computer readable medium that cause a computer, when theprogram instructions are loaded into a memory of the computer, toexecute a process for suppressing adjacent channel interference (ACI)and adjacent leakage interference (ALI) in a full-duplex cable modem,the process comprising: converting a digital upstream (US) signal intoan analog US signal in a US frequency range; receiving an analogdownstream (DS) signal in a DS frequency range; analog filtering thereceived DS signal; digitizing the analog-filtered DS signal; tappingthe transmitted analog US signal; digitizing the tapped analog USsignal; and digitally subtracting from the digitized DS signal at leasta portion of the digitized US signal.
 19. The computer program of claim18, wherein analog filtering comprises subtracting from the receivedanalog downstream DS signal a digitally processed analog correctionsignal derived from the converted analog US signal.
 20. The computerprogram of claim 18, wherein analog filtering comprises subtracting fromthe received analog downstream DS signal an analog correction signalderived from the digital US signal, wherein the digital US signal isprocessed in a DSP before being converted to the analog correctionsignal.